`timescale 1ns / 1ps
`include "const_def.vh"

module beq_judge(
        input   [31:0]  num1,
        input   [31:0]  num2,

        output  [3:0]   ctrl_beq_z,
        output  ctrl_beq
    );

    assign  ctrl_beq = (num1 == num2) ? `CTRL_BEQ_EQ : `CTRL_BEQ_NE ;
    assign  ctrl_beq_z =
            (num1 > 0)  ? `CTRL_BEQ_GTZ :
            (num1 < 0)  ? `CTRL_BEQ_LTZ :
            (num1 <= 0) ? `CTRL_BEQ_LEZ :
            (num1 >= 0) ? `CTRL_BEQ_GEZ : 4'b0000;

endmodule
